1. Field of the Invention
The present invention relates to driver stages for driving an output on one of n-levels, as may be used for example in multi-level signaling.
2. Description of the Prior Art
Multi-level signaling enjoys a growing interest with respect to bus interfaces having a high bandwidth. Multi-level signaling techniques, in which two bits are simultaneously transmitted to a clock cycle and/or a clock edge, currently take a different stand. In order to achieve this, the bus is driven to one of four different levels, which may then be decoded on the receiver-side by a simple two-bit analog/digital conversion.
The U.S. Pat. No. 6,140,841 describes a high-speed interface device comprising a data driver means for decoding 2-bit data signals so as to obtain 4-level data signals, a reference voltage generation means for generating multi-level reference voltages so as to be able to differentiate between the voltage levels of the 4-level data signals, and a receiving means for simultaneously comparing the 4-level data signals with multi-level reference voltage signals, so as to output 2-bit data signals, depending on the comparison. An example of a data driver means includes three n-channel MOS-transistors connected in parallel between ground and the transmission line, which is biased via terminal resistors on a terminal voltage. The channel widths of the transistors are 2WN each. By turning the respective transistors on and off, the total channel width is changed step-wise by 2WN, as a result of which the driving current and the driving voltage on the transmission line are equidistantly changed on a step-wise basis. Each of the resulting four possible voltage values and/or voltage levels is associated with a combination of bit values of the 2-bit data signals. The reference voltages will be set to the voltages which are located in the center between the possible four voltage levels. A further example for the data driver means provides two p-channel MOS-transistors connected in parallel between the supply voltage and the transmission line and two n-channel MOS-transistors connected between ground and the transmission line. The transistor width of one of the pairs of transistors each is two times the size of the one of the other one of the respective pairs of transistors. By turning the transistors on and off, four different voltage levels are generated which are arranged equidistantly to each other by a voltage difference.
A disadvantage of the high-speed interface device of the U.S. Pat. No. 6,140,841 is that when using this device, either serious transmission errors occur or complex adjustments of the reference voltages are necessary, so as to avoid these transmission errors.